1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same. More particularly, the present invention relates to a highly integrated semiconductor device and method of fabricating the same.
2. Description of the Related Art
With the development of the electronics industry, including mobile communications and computers, semiconductor devices with rapid read/write speed, nonvolatility, and a low operating voltage have become very desirable. However, conventional memory devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory, do not satisfy all of these requirements.
For example, since a unit DRAM cell of includes a single capacitor and a single transistor for controlling the capacitor, it requires a greater area than a unit cell of a NAND flash memory. Also, the DRAM, which stores data in the capacitor, is a volatile memory device that needs a refresh operation, as is well known. The SRAM operates at high speed, but is also one of volatile memory devices. Moreover, a unit cell of the SRAM is comprised of 6 transistors, so it occupies a large area. Flash memory, a nonvolatile memory device, has the highest integration density of present memory devices, especially the NAND flash memory. However, it operates at a relatively low speed.
For these reasons, there have been extensive studies on new memory devices, e.g., phase-random access memories (PRAMs), which may operate at low voltages, may be capable of fast read/write operations, exhibit nonvolatility, and need no refresh operation.
FIG. 1 illustrates a cross-sectional view of a conventional PRAM.
Referring to FIG. 1, the conventional PRAM may include a phase-change pattern 40 provided between a source line 70 and a bit line 50, which intersect each other. The PRAM may sense a change in resistance of the phase change pattern 40, relative to the crystalline state of the phase-change pattern 40, and determine stored data based on the resistance. The crystalline state of the phase-change pattern 40 may be changed by controlling a current flowing through the phase-change pattern 40. In order to control the current and sense the change in resistance, the PRAM may include a transistor on a semiconductor substrate 10.
The transistor may include a gate electrode 20 disposed on the semiconductor substrate 10 and source and drain regions 30 disposed on both sides of the gate electrode 20. The source and drain regions 30 may be connected to the phase-change pattern 40 and the source line 70.
A unit cell of such a PRAM may employ one transistor disposed on the semiconductor substrate 10 and one phase-change pattern 40 disposed to one side of the transistor. As a result, it may have almost the same area as a unit cell of a DRAM. Therefore, although exhibiting otherwise excellent characteristics for an advanced memory, this conventional PRAM may not be any more highly integrated than a DRAM.
FIG. 2 illustrates a cross-sectional view of a second conventional PRAM. Referring to FIG. 2, the second PRAM includes the phase-change pattern 40 provided between the source line 50 and the bit line 70, which intersect each other as in the PRAM shown in FIG. 1. A diode, which controls a current flowing through the phase-change pattern 40, may be interposed between the phase-change pattern 40 and the source line 70. The diode may include impurity regions 62 and 64 having different conductivities. As is well known, the diode allows an electric current to flow in one direction, but essentially blocks it in the opposite direction. Thus the diode may be used to prevent formation of an electric path to an unselected cell.
In the second conventional PRAM, the source line 70 may be interposed between two adjacent diodes as shown in FIG. 2. A unit cell of the second PRAM may occupy an area smaller than that of the PRAM having the transistor described above with reference to FIG. 1. However, the area of the second PRAM may still be greater than that of a flash memory device. More specifically, the smallest area of the unit cell of the PRAM shown in FIG. 1 may be about 15 F2, the smallest area of the unit cell of the PRAM shown in FIG. 2 may be about 7 F2, and the area of a unit cell of a typical NAND flash memory device may be about 4 to 5 F2, where, “F” refers to a feasible minimum feature size.
A diode formed using a single-crystalline semiconductor may provide excellent and stable electrical characteristics. However, forming the diode using a single-crystalline semiconductor is an obstacle to further reducing the area of the unit cell of the PRAM shown in FIG. 2, and conventional techniques do not provide suitable methods for overcoming this obstacle. In particular, when a semiconductor layer, such as a silicon layer, is formed using a deposition process, the semiconductor layer may not be in a single-crystalline state. Rather, the deposited layer may be in an amorphous or polycrystalline state. Although there are some methods, e.g., an epitaxial growth method, of growing a single-crystalline layer directly on a single-crystalline substrate, e.g., a single-crystalline semiconductor substrate, a method of crystallizing a layer spaced apart from the substrate so as to form a single-crystalline structure has not been proposed.